A flash memory device utilizes an array of flash memory cells to store data. Prior Art FIG. 1 is a cutaway view of a typical flash memory cell 100, consisting of a control gate 101, a charge trapping layer 102, e.g. an oxide-nitride-oxide (ONO) stack, an oxide film 103, a channel region 104, and doped regions 105a and 105b. One of the doped regions 105a can be designated as the source for the cell, and the other doped region 105b can be designated as the drain for the cell. The role of the doped regions 105a and 105b (source or drain) is interchangeable depending on the outcome desired. The control gate 101, floating gate 102 and oxide film 103 are stacked on top of the substrate 106, while the channel 104 and doped regions 105a and 105b are situated within the substrate. The control gates 101 of flash memory cells 100 in a row are connected by a word line 110.
Prior Art FIG. 2 is diagram of a conventional array of flash memory cells. The memory cells 100 in a row 215 in the array 200 are connected by a word line 110, and the word lines 110 are controlled by a word line driver 211. Columns 225 of memory cells 100 in the array 200 are also accessed by bit lines 220. The bit lines 220 are controlled by a bit line driver 221. Each bit line 220 is shared by two adjacent columns 225 of memory cells 100 in the array 200.
In single bit flash memory architecture, each memory cell 100 can represent two states: binary 1 or binary 0. Referring to Prior Art FIG. 1, if a cell 100 is “turned on,” current can flow through the channel 104, and the cell reads as “1.” If the cell 100 is “turned off,” a read current cannot flow through the channel, and the cell reads as “0.” Single bit flash memory cells store 1 bit per cell. Programming of a flash memory array 200 begins with every cell in the same state, either 1 or 0. If all cells 100 are initially in the 1 state, in other words all cells 100 in the array 200 are turned on, programming consists of changing selected cells to the 0 state, i.e. turning them off. Conversely, if all cells are initially in the 0 state (turned off), programming consists of changing selected cells to the 1 state (turning selected cells on). A read operation can then be performed on the array to mine the binary data from the array of cells. Before the next program operation, the flash memory cells are erased, or returned to their initial state, and programming begins again. Flash memory cells can be programmed (written) and erased repeatedly during the lifetime of the flash memory device.
Referring back to Prior Art FIG. 1, to read a single bit flash memory cell 100, a read voltage (e.g. 3V) is applied to the control gate 101 via the word line 110, a secondary voltage (e.g. 1.4V) is applied to the drain 105b, and the source 105a is grounded. The resulting current flowing from the source 105a to the drain 105b through the channel 104 is measured and compared to a reference current. If the measured current is above the reference current, the cell reads as “1,” and if the measured current is below the reference current, the cell reads as “0.”
Still referring to Prior Art FIG. 1, to create the “0” state of a single bit cell 100, the threshold voltage of the cell is raised by applying a high positive voltage (e.g. 9V) to the control gate 101, a positive voltage (e.g. 5V) to the drain 105a, and grounding the source 105b. The voltage potential of this configuration excites electrons in the channel 104 to accumulate near the drain 105a and then pierce the oxide film 103 and get trapped in the charge trapping layer 102 of the cell. The electrons remain trapped in the charge trapping layer 102 even after the high voltage is no longer applied to the control gate 101. When a read operation is performed on a cell in this state, the cell reads as “0.” In other words, the measured current through the channel 104 is less than the reference current.
Still referring to FIG. 1, to create the “1” state of a single bit cell, in other words to turn on a cell that is off, the threshold voltage of the cell 100 is lowered by applying a low or negative voltage (e.g. −6V) to the control gate 101 and a positive voltage (e.g. 5V) to the source 105a and the drain 105b. The voltage potential of this configuration forces electrons to tunnel through the oxide film 103 and down into the substrate 106. When a read operation is performed on a cell 100 in this state, the cell 100 reads as “1.” In other words, the measured current through the channel 104 is greater than the reference current.
Typically, when electrons are trapped in the floating gate 102 of a flash memory cell 100, they tend to remain on the side of the floating gate 102 above the drain (e.g. 105b) of the cell 100. Due to this phenomenon, it is possible to store two bits of information in a flash memory cell 100 in what is called dual bit, or mirror bit flash memory.
Referring now to Prior Art FIG. 3A, the threshold voltage of a cell 100 is raised by applying a high voltage (9V) to the control gate 101 via the word line 110, designating the left doped region 105a as the source and grounding it, and designating the right doped region 105b as the drain and applying a positive voltage (5V) to the drain 105b. Electrons 301 are trapped in the right side of the charge trapping layer 102. Subsequently, as depicted in Prior Art FIG. 3B the source and drain regions can be reversed, e.g. the left doped region 105a designated as the drain and given the positive voltage (5V) and the right doped region 105b designated as the source and grounded. Consequently, electrons 302 are trapped on the left side of the floating gate 102.
When a read operation is performed on a dual bit flash memory cell 100, there are four possible states that can be represented. If there are no electrons trapped in the floating gate 102, the threshold voltage of the cell 100 is at its minimum, the measured current is at its maximum, and the cell is read as “11.” If there are electrons (301, 302) trapped in one side of the floating gate 102 but not the other, the cell reads as either “01” or “10.” The measured current through a “01” cell is distinct from the measured current through a “10” cell. If electrons (301 and 302) are trapped on both sides of the floating gate 102, the threshold voltage is at its maximum, the measured current is at its minimum, and the cell 100 reads as “11.”
When operations are performed on one cell 100, the states of neighboring cells 100 tend to be disturbed. For example, when the threshold voltage of cell A 230 is raised to the desired level, the threshold voltage of neighboring cell B 240 along the row 216 might inadvertently raise. This disturbance leads to read and write errors. Dual bit cells are especially susceptible to disturbance, as there are four possible threshold voltage distributions that must be distinct and separate from one another. Conventional flash memory methods incorporate remedies for inhibiting or preventing disturb on neighboring cells.
A conventional method of flash memory programming consists of starting with an array 200 of cells 100 in the “1” state in a single bit architecture or “11” in a dual bit architecture, designated as the “erased” state. In other words, in an erased array 200, according to conventional methods, the cells are turned on. Selected cells are programmed by raising the threshold voltages of the selected, so that selected cells read as “0” in single bit architecture or “01,” “10,” or “00” in dual bit architecture.
A page 250, depicted in Prior Art FIG. 2, in flash memory is the amount of flash memory cells 100 that can be programmed at once. Writing, or programming a cell 100 requires a certain current. Page size is dictated by the maximum current that can be applied to the array 200 at one time, and how many bits can be programmed with that current. According to conventional methods of flash memory, pages 250 are typically oriented in the row direction. In other words, cells 100 are programmed row by row. A high voltage is applied to the control gates 101 of a row 215 of cells 100 via the word line 110 connecting these cells 100, and voltages are applied to the bit lines 220 as required to raise the threshold voltage on each cell 100 by the desired amount, thereby programming selected cells in the page 250. In this scenario, approximately 250 μA is required to program a dual bit cell, and a typical page size is 8 bits, programmed at a rate of approximately 5 μsecs per page (0.20 kB/msec).
One characteristic of flash memory is that cells are erased in blocks to conserve time. In a conventional method, erasing a block means to return a block of cells to their “1” or “11” state, in other words restoring a block of cells to the “on” state, by lowering the threshold voltages on all the cells in the block at once.
Conventional mirror bit architecture is non-volatile and is suitable for long term code storage and other read-only applications. Due to the long programming time, conventional mirror bit architecture is not suitable for re-writable data storage, for example data storage arrays used in digital cameras.
In the field of flash memory, there is a constant desire to increase programming speed while maintaining efficient read speeds and the non-volatile nature of the data storage and keeping changes to fabrication processes to a minimum.